Vertical field effect transistors (VFETs) are becoming viable device options for complementary metal oxide semiconductor (CMOS) devices beyond 7 nm node. VFET devices include fin channels with source/drain regions at ends of the fin channels on top and bottom sides of the fins. Current runs through the fin channels in a vertical direction (e.g., perpendicular to a substrate), for example, from a bottom source/drain region to a top source/drain region.
A typical semiconductor chip has a variety of circuits. Some circuits may include transistors that share a gate, where, for example, two adjacent VFETs have different fin channels but share the same gate. The shared gate may be physically connected at a gate level so that only a single gate contact is needed for both transistors. Other circuits may have separate gates, meaning two gates electrically isolated from each other, one gate for each respective transistor. A minimal distance between two adjacent gates is required to accommodate inherent process variations, but adversely impacts device density.